Silicon-on-insulator (SOI) devices offer several advantages over more conventional semiconductor devices. For example, SOI devices may have lower power consumption requirements than other types of devices that perform similar tasks. SOI devices may also have lower parasitic capacitances than non-SOI devices. This translates into faster switching times for the resulting circuits. In addition, the phenomenon of “latchup,” which is often exhibited by complementary metal-oxide semiconductor (CMOS) devices, may be avoided when circuit devices are manufactured using SOI fabrication processes. SOI devices are also less susceptible to the adverse effects of ionizing radiation and, therefore, tend to be more reliable in applications where ionizing radiation may cause operation errors.
A drawback in some SOI circuits is the floating body effect. Due to the additional isolation of the SOI device, the body or well node is not typically contacted. In principal, body tie structures may be employed in SOI CMOS to add a contact to the floating body node, but this introduces parasitic resistances and capacitances which would negate the favorable impact of adaptive well biasing.
For many digital circuits, this impact can be neglected. However, certain circuit array cell stability, such as the commonly used 6T SRAM cell, is degraded due to tolerance issues arising from the floating body. This is typically handled with increasing the linear threshold voltage (Vt) of the FETs in the array, but this is usually at the cost of lowering the overall array performance.
A recent innovation, hybrid orientation CMOS technology (HOT) uses both SOI nFETs and pFETs and conventional bulk nFETs and pFETs (see, for example, M. Yang, et al., IEDM 2003, p. 453 and U.S. application Ser. No. 10/250,241, filed Jun. 17, 2003, entitled “High-Performance CMOS SOI Devices on Hybrid Crystal Oriented Substrates”). 
Additionally, the same or different crystallographic orientations can be used for nFET and pFET devices. The use of different crystallographic orientations allows for independently optimizing the performance of an nFET (which in silicon has highest mobility and performance in the (100) orientation) and the pFET (which in silicon has the highest mobility and performance in the (110) orientation). Additionally, it is known within the art, that nFET devices formed atop a (110) crystal plane have decreased carrier mobility and switching speed. With the availability of hybrid bulk-SOI CMOS or hybrid orientation (HOT) bulk-SOI CMOS, the opportunity exists to place some of the array devices in bulk CMOS. In all cases, the elimination of the floating body effect in a portion of the cell will reduce the need for linear Vt increases and will provide for better cell stability and performance. Additionally, the contact to the well region for some of the devices permits the use of adaptive well biasing (see, for example, J. Tschanz, et al., J. Solid State Circuits, 2002, p.1396.), through which the Vt's of FETs in this region may be controlled by adjusting the well node bias value. Adjusting the Vt's dynamically could be used in arrays to reduce power in a processor sleep mode (by raising the Vt's in this mode) or to increase performance when the array is being accessed (by lowering the Vt's in this mode).
In view of the above, there is a need for providing a hybrid bulk SOI 6T SRAM cell that exhibits improved cell stability and performance wherein adaptive well biasing is employed.